1. Field of the Invention
The present invention generally relates to a semiconductor device and an electronic apparatus using the semiconductor device.
2. Description of the Related Art
In electronic apparatuses such as portable telephones and portable terminals, attainment of a plurality of functions in a compact size is demanded. For this purpose, a technique of mounting a plurality of circuits for the plurality of functions using a plurality of power supply voltages on one chip has been developed, as described in, for example, Japanese Laid Open Patent Application (JP-P2002-83872A) and a leaflet issued from Japan IBM company, and retrieved on Jun. 11, 2004 through the Internet URL: http://www6.ibm.com/jp/chips/literature/pdf/CullASIC.pdf>
FIG. 1 is a plan view schematically showing a conventional semiconductor device 200 using power supply voltages. Referring now to FIG. 1, the conventional semiconductor device 200 contains an internal logic circuit 201 and an input/output circuit region 202. In the input/output circuit region 202 of this conventional semiconductor device 200, an outside region of a boundary indicated by a broken line is an external power supply region where a power supply is normally turned ON. Also, an inside region of the boundary indicated by the broken line is an internal power supply region. When the internal logic circuit 201 operates, the power supply is turned ON, whereas when the internal logic circuit 201 does not operate, the power supply is turned OFF. In the input/output circuit region 202, level shifters 211 and 213, buffers 212, 213, and 214 are arranged. The level shifter 211 level-shifts a signal from the internal logic circuit 201, and outputs the level-shifted signal to an external circuit via a terminal 223. The buffer 212 outputs a signal from the internal logic circuit 201 to the external unit via the terminal 223 without any level shift. The level shifter 213 level-shifts a signal supplied from the external circuit via the terminal 223 and transfers to the internal logic circuit 201. The buffer 214 outputs a signal supplied from the external circuit via the terminal 223 to the internal logic circuit 201 without any level shift. As described above, the internal logic circuit 201 outputs and receives the signals via the input/output circuit region 202 with respect to the external circuit.
In the above-described semiconductor device 200, when the internal logic circuit 201 is not used, the supply of the electric power to the internal logic circuit 201 is stopped, so that power consumption can be reduced. However, when the supply of the electric power to the internal logic circuit 201 is stopped, signals voltages become uncertain in the internal logic circuit 201. As a result, the below-mentioned troubles may occur. That is, a signal with an uncertain level is supplied from the internal logic circuit 201 to the level shifter 211. Therefore, a leak current flows. Also, a gate leak occurs in the buffer 214 which receives the signal from the external circuit. Because of these leak currents, even if the supply of the electric power to the internal logic circuit 201 is stopped, the power consumption is not reduced. Therefore, an effect when the supply of the electric power to the internal logic circuit 201 is stopped cannot be so much expected.
Japanese Laid Open Patent Application (JP-A-Heisei 10-84274) discloses a semiconductor logic circuit and a circuit layout structure in FIG. 11 of the application. In this conventional example, it is described in a paragraph number [0104] that a low-voltage power supply wiring line and a control wiring line (control terminal) for a power converter are previously provided in each of input cells, output cells, and other power supply cells, and wiring is completed only by arranging the cell. Also, it is described in a paragraph number [0102] that when a logic circuit is in a sleep state, a control circuit outputs a control signal to stop the supply of internal power from an external circuit outside a semiconductor device, for reduction of power consumption. Also, it is described that when the logic circuit is in an active state, the control circuit outputs another control signal to supply the internal power. Therefore, in this conventional example, the control circuit would contain any section for determining whether the logic circuit is in the sleep state or the active state, and control the supply of the internal power in accordance with the determination result.
In conjunction with the above description, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-74348). In the semiconductor device of this conventional example, a first inverter is connected between a first power supply terminal for a first voltage and a second power supply terminal for the ground potential. A boosting circuit is connected between a second power supply terminal for a third voltage and the second power supply terminal, and operates based upon an input signal and output signal of the first inverter. A second inverter receives an output signal of the boosting circuit, and operates in the second voltage. A switch is connected between the boosting circuit and either the second power supply terminal or the third power supply terminal, and operates to control the operation of the boosting circuit. As a consequence, even when the first voltage is brought into the ground potential, the leak current is prevented.
Also, Japanese Laid Open Patent Application (JP-P2004-128590A) discloses a level shift circuit. In the level shift circuit of this conventional example, an input circuit receives a signal from a low voltage circuit. An output circuit contains a latch circuit, and holds an output signal to a high voltage circuit. A first switch circuit stops the output of the signal from the input circuit to the output circuit in response to a control signal. A second switch circuit stops the supply of power to the output circuit except for the latch circuit in response to a control signal. Thus, the level shift circuit prevents a leak current.
Also, Japanese Patent No. 3498090 discloses a semiconductor device. In this conventional example, an electronic circuit contains a first MOS transistor of a first conductive type having a source-to-drain path between a first potential point and a second potential point, and a source connected to the first potential point. A second MOS transistor of the first conductive type has a source-to-drain path between a third potential point and the first potential point, and a source connected to the third potential point. A control signal is supplied to a gate of the second MOS transistor. When the control signal is set to a first state, the second MOS transistor is set to an ON state, to allow a current to flow between the first potential point and the second potential point via the source-to-drain path of the first MOS transistor in the ON state. When the control signal is set to a second state, the second MOS transistor is set to an OFF state, to restrict a sub-threshold current flowing between the first potential point and the second potential point via the source-to-drain path of the first MOS transistor in the OFF state based upon the characteristic of the OFF state of the second MOS transistor. An operating voltage which is determined based on the third potential point and the second potential point is applied from an internal voltage downing circuit.